In an Solid State Device (SSD) adapter which does data compression, several Logical Block Addressed blocks (LBAs) can be bundled together to form a much bigger unit (e.g., a data chunk). This unit can be then run through a compression engine on the adapter which can make the compressed LBA blocks take up much less space than if they were stored in their natural size. This compressed data chunk is then stored on the SSD (e.g., on NAND type flash memory). The size reduction can be 50% or more. This means several LBA blocks can be stored as a single unit in flash memory. When these LBA blocks are accessed to read, the compressed data chunk must be retrieved from the flash memory and then decompressed. Out of all the decompressed LBA blocks potentially only a single LBA block is needed to satisfy the read request.
Peripheral Component Interconnect Express (PCIe) is frequently used to connect SSDs to a host system. PCI-Express system architecture faces a performance constraints. First, typical PCI-Express fabrics with high device fan-out (such as an enterprise storage backplane) have lower total upstream bandwidth (from a PCI-Express Switch upstream to the host) than downstream bandwidth (from the same PCI-Express Switch downstream to all connected storage controllers). This may present a bottle neck at a PCIe switch if bandwidth of downstream resources is greater than upstream bandwidth. Such a bottleneck may delay retrieval of read results from an SSD to a host device.